The present invention relates to a logic circuit which is commonly called a CML (Current Mode Logic) circuit.
A CML circuit comprising bipolar transistors as its basic components is known as being one of the highest speed devices available at the present time. An ECL (Emitter Coupled Logic) circuit comprising emitter follower transistors as its basic components and operating with a logical amplitude of 0.8 V has heretofore been known to be one of logic circuits operable at a high speed. The remarkable progress in the semiconductor integrated circuit technique in recent years has led to the realization of circuit integration at a higher packaging density and has been successful in reducing noise to a level far lower than that of conventional logic circuits of this kind. Thus, it is now possible to provide a low-amplitude logic circuit in which the logical amplitude is reduced to about 0.4 V from the previous value of 0.8 V. The low amplitude eliminates the problem of transistor saturation, and the emitter follower transistors are now unnecessary. However, difficulties have arisen in such CML circuits in compensating for power supply variations and junction temperature dependency. These problems have heretofore hampered the utilization of such CML circuits.